The most power efficient CMP consists of low power in-order cores.
However, performance on such a processor is low unless the workload is nearly completely parallelized, which depending on the workload can be impossible or require significant programmer effort.
A reconfigurable multiprocessor system including a number of processing units and components enabling executing sequential code collectively at processing units and enabling changing the architectural configuration of the processing units.a plurality of processor units, wherein the plurality of processor units are independent cores and dynamically fused into a single processor, wherein the single processor is dynamically split into distinct processing units at run time; andat least one cross unit connection component operatively connecting at least two processor units from said plurality of processor units, said at least one cross unit connection component reconfigurably linking one processor unit to another processor unit, thereby fusing them as a single processor, said reconfigurable linking adjusting processing to sequential when in a fused mode and to parallel when in a split mode; said at least one cross unit connection component enabling collective fetching and providing instructions to be executed collectively by said at least two processor units and collectively committing executed instructions by said at least two processor units; said collective fetching comprising cooperatively fetching an instruction block; said instruction block comprising a number of subsets, said fetching being performed cooperatively by fetching a one subset of said instruction block by each of said at least two processor units, when the processor units are in the fused mode; said instruction block comprising each subsets of instructions fetched by each of said at least two processor units; said instruction block being constructed from each subset of instructions fetched by each of said at least two processor units; said collective fetching enabling operation of said at least two processor units substantially as a single processor unit; whereby executing sequential code collectively at processor units is enabled; andwhen changing manner of processing from fused to split or from split to fused, bringing an internal state of said plurality of processing units to a form consistent with a new configuration, resulting from the reconfiguring of cross connection unit, andsaid at least two processor units from said plurality of processor units and enabling reconfigurably linking one processor unit to another processor unit, and of enabling collective fetching and branch prediction; a second cross unit connection component reconfigurably and operatively connected to said at least two processor units from said plurality of processor units, said second cross unit connection component enabling steering and renaming instructions for/from each processor unit;a third cross unit connection component reconfigurably and operatively connecting said at least two processor units from said plurality of processor units and enabling transfer of output instruction values from one processor unit as input instruction values to another processor unit;a fourth cross unit connection component reconfigurably and operatively connecting at least two processor units from said plurality of processor units, said fourth cross unit connection component enabling transferring signals between reorder buffer memories in processor units from said plurality of processor units, and of enabling collective instruction commit.a fetch management component operatively connected to said first cross unit connection component, said fetch management component enabling coordinating distributed operation of fetch components in each processor unit.a steering management component enabling steering and renaming instructions for/from each processor unit; and said steering management component being operatively connected to each processor unit through said second cross unit connection component.6.
Improving the performance of computer or other processing systems generally improves overall throughput and/or provides a better user experience.
One technique of improving the overall quantity of instructions processed in a system is to increase the number of processors in the system.
FCMPs introduce a new resource allocation and scheduling problem which must determine how many logical processors should be configured, how powerful each processor should be, and where/when each task should run.
This paper introduces and motivates this problem, describes the challenges associated with it, and evaluates algorithms appropriate for multitasking on FCMPs.
The goal of power management is to maximize performance within a given power budget. His major research interests are Artificial Intelligence such as Genetic Algorithms, Neural Networks, Particle Swarm Optimization, Simulated Annealing, and Fuzzy Logic.
Power management techniques must balance between the demanding needs for higher performance/throughput and the impact of aggressive power consumption and negative thermal effects. Also he is interested in the application of AI in Machine Learning, Image Processing, access control and Optimization.
The main objective of this paper is to survey and discuss the current power management techniques. in 2013 with an overall grade of excellent with honors from Mansoura University. Professor at Computers Engineering and Control systems Dept.––Faculty of Engineering––Mansoura University, Egypt.
Moreover, it proposes a new technique for power management in multi-core processors based on that survey. Attia is a teaching assistant at Computers and Control Systems Engineering Department, Mansoura University. His main research interests include Computer Architecture and Organization, Heterogeneous Multi-Core Architectures, Power-aware computing and Heterogeneous Parallel Programming.
Implementing multiprocessing (MP) systems, however, typically requires more than merely interconnecting processors in parallel.